1. Technical Field
The present invention relates to a CMOS structure, and more particularly to a CMOS structure with minimized latch-up. The present invention also relates to a method for reducing latch-up effect of a CMOS IC.
2. Description of the Related Art
A so-called latch-up effect commonly occurs in an integrated circuit (IC) such as a complementary metal oxide semiconductor (CMOS) device. Latch-up might damage the IC as causing the creation of a PNPN path through which a high current is generated. CMOS device manufacturers have been endeavoring to ameliorate the latch-up effect.
Please refer to FIG. 1A, which schematically illustrates a CMOS IC in a cross-sectional view. As shown, a pad 14 for an input pin 15 is coupled between a PMOS portion 10 and an NMOS portion 18 via a P-well region 12 and an N-well region 13. With such a configuration, a path originating from VDD and passing through the P+ region 100 in the PMOS portion 10, another N-well 11 underneath the PMOS circuit, the P-well 12 and the N-well 13, which is a PNPN path, may be conducted and undesirable reach the pad 14. When the input pin 15 is at a low level, a high current likely flows through the above-described path and the latch-up effect is thus rendered. For ameliorating the damage, an improved CMOS IC structure is shown in FIG. 1B in a cross-sectional view. As shown, a P+ region 19 is additionally provided above the P-well region 12. Accordingly, a high current, if occurring, can be drained through the P+ region 19 so as to avoid latch-up.
The above solution, unfortunately, cannot be applied to a CMOS IC manufacturing process involving a so-called 1P1M process, i.e. one poly one metal process, since there is no way to form a conductor capable of connecting the P+ region 19 to the external.